The present invention relates to a process for manufacturing microelectronic circuitry for printed wiring boards especially with regard to laminate chip carriers. This semi-additive process allows the fabrication of high density circuitry on printed wiring boards having high-aspect plated through holes in high yield with minimal manufacturing steps.
As is well known in the art, miniaturization of computer components is a highly desirable goal and this demand has and will continue to dictate the requirement for continually smaller and smaller microelectronic components on packages such as printed wiring boards and laminate chip carriers. Typically, manufacturers employ three technologies for fabrication of such microelectronic components. These include the many varieties of subtractive, semi-additive, and full additive processes for fabricating fine line circuitry on printed wiring boards. Each of these processes has known difficulties and limitations with regard to producing high quality, high density fine-line circuitry.
The subtractive process requires that a full panel plating of copper be employed followed by imaging and developing of an overcoated resist layer and then etching of the copper in areas where the resist was removed. Major problems associated with this process include the fact that large amounts of copper must be etched away and that it is common for undercutting of the remaining circuitry to occur, especially the well known galvanic etching in areas where noble metals are present in proximity to the copper circuitry. There is also the problem of insufficient resolution using the subtractive process, this significantly limits the ultimate density of the fine line circuitry, for example it is well known that as the line or space dimension approaches the thickness of the layer to be etched, subtractive etching becomes unacceptable. To remedy this situation the etch mask must be made larger than the desired feature to allow for this lateral etching.
To circumvent these problems associated with the subtractive process (viz., large waste streams of etch materials and poor resolution due to lateral etching) the additive process has been employed. However, in the case of the additive process, problems are encountered with the need for an adhesion promoting seed layer that must be applied after the photoresist is imaged. This seed layer covers not only the desired areas to be plated but also covers the top surfaces of the photoresist layer. This could cause copper to be plated in areas not desired to be plated. To circumvent this problem, the topmost portions of the photoresist must be chemically or mechanically cleaned of the seed layer. Mechanical etching of this seed layer is known to cause physical defects in the final product due to minute particles causing conductive junctions between what should have been discrete circuit lines. Another potential defect caused by mechanical cleaning is the stress placed on the microcomponent which potentially can cause delamination. Lastly, the process itself is quite expensive due to the required buildup of copper microcircuitry via electroless plating.
To address the problems associated with both the additive and subtractive processes and to further provide electrical continuity to both sides of the substrate, a xe2x80x9csemi-additivexe2x80x9d process has been utilized by industry in order to make fine line high density printed wiring boards. One variant of this prior art process employs the following steps:
a) imparting an adhesion promoting process on the surface of the substrate package, typically including applying an adhesion promoting layer of a rubber-like material,
b) applying a thin copper foil to the uppermost surface of the adhesion promoting layer,
c) drilling the foiled substrate to create through holes either for the purpose of connecting microcircuitry on the opposing sides of the substrate or for mounting sites for other microelectronic components,
d) electroless plating a thin copper layer to the through-holes and uppermost surface(s) of the foiled substrate,
e) coating the uppermost surface(s) of the copper-clad substrate with a resist that is then exposed and developed to generate vias to the underlying copper layer,
f) electroplating additional copper into these vias to form the desired microcomponent features,
g) removing the remaining photoresist, and
h) etching the now uncovered, original thin copper layer and underlying copper foil to create the discrete microcomponents features and plated through holes.
The semi-additive process as practiced in the art still suffers from several problems. When either sputtering or copper foil was used as the method of applying the initial thin copper layer, the through holes would be untreated and therefore would still have essentially the insulated surface of the resin or glass substrate. This is especially true for high aspect through holes (i.e., thickness of the resin substrate is greater than 5 times the diameter of the through hole). Therefore, additional manufacturing steps were required for preparing those surfaces for plating. As described above, electroless plating of the through holes has been performed after foil lamination but problems have been encountered with adhesion between the electroless copper film plating and the copper foil. Prior art teaches the need to abrade or buff the copper foil before electroless plating in order to ensure good adhesion in the final package. The minimum thickness of the copper foil that can be applied in the semi-additive process is limited by handling problems during the lamination process and this minimum thickness is larger than would be desired in order to create extremely fine line features.
Furthermore, prior art electroless plated layers were still too thick to allow highly dense microelectronic circuitry to be prepared due to the fact that etching as known in the art is largely isotropic and therefore the etch will progress horizontally virtually to the same extent that it will occur vertically. Therefore, the thicker the layer to be etched, the wider the spacing between the features must be otherwise undercutting will become significant and adhesion problems result. In an ISandT article (1970), Celestre and Heiart described a process that involved electroless copper plating of an insulating support to give a conductive layer thickness of 0.3 mil (300 microinches). A resist is then applied, imaged and the circuit lines plated up to a thickness of 1.5 mil. Then the circuits are overplated with nickel and gold. After stripping away the resist, the electroless copper is etched away to complete the circuit panel. As can be seen in this prior art example, the initial electroless layer is approximately 20% of the thickness of the final thickness of the circuitry. As this electroless layer or foil becomes a significant percentage of the total circuit thickness, the semi-additive process in essence takes on the problematic characteristics of the subtractive process. Etching this amount of unwanted copper is not only wasteful and expensive but the process itself will cause significant undesirable lateral etching of desired circuit features. Lateral etching, therefore,- limits the density of the copper circuitry by increasing both the minimum practical line width and the smallest acceptable space between features. This is true even when, as in the case cited, a metal mask such as gold/nickel is employed to protect features from attack.
Widespread use of the semi-additive process where features are plated directly onto the insulating substrate has been limited by poor adhesion between the substrate and the copper. It is desirable to obtain a printed wiring bandwidth the greatest xe2x80x9cpeelxe2x80x9d strength. Stahl, in U.S. Pat. No. 3,625,758, describes a semi-additive process in which a insulative base substrate material, such as phenolic paper board is brushed or sanded to clean and roughen the surface and treated with suitable activating solutions for the electroless deposition of copper. Stahl reports that a serious drawback of lack of sufficient bond between the surface of the base material and the copper conductors exists. To reduce this problem, Stahl employs -an adhesive layer between the insulative base and the copper conductive layer. This package must then be heat treated and pressed to ensure sufficient adhesion.
Many other approaches have been used to alleviate this problem, but typically these either add complexity to the manufacturing process or require additional raw materials. For instance, Mersereau discloses, in U.S. Pat. No. 3,854,973, treating a base substrate in an organic solvent such as dimethyl sulfoxide followed by immersion in an appropriate chromic sulfuric acid oxidizing solution and thereafter catalyzing the surface with an appropriate electroless plating catalyst. Mersereau also employs a noble metal, overcoating the circuitry and also still recommends a baking process to effect acceptable bonding.
Polichette in U.S. Pat. No. 3,930,963, discloses an additive process for manufacturing printed wiring boards which commences with an epoxy glass laminate base material which is put through a series of chemical treatment steps, including: treatment in an absorber, drying, rinsing, punching holes, pre-activation, draining, oxidizing, and reducing to render the board surface microporous. This is followed by removing excess agents, poisoning, and applying a layer of a reducible metal compound.
Cross, in U.S. Pat. No. 4,217,182, describes the use of a semicured adhesive material applied as a layer between the dielectric support and the conductive layer. In this patent Cross describes the steps required to electrolessly plate copper onto a dielectric substrate. Starting with the untreated substrate, twelve steps were required from application of the adhesive layer to electroless plating. Cross does teach the use of a very thin electroless copper layer on the order of 15-50 microinches and this is an advancement to the art but overall the process is long and cumbersome.
Ogasawara, et al., in U.S. Pat. No. 5,044,073, describes a semi-additive process that is used to fabricate a printed wiring board. This process utilizes a two step activation process that includes a catalyzing treatment comprising a material OPC-80 and accelerating treatment comprising a material OPC-555 prior to electroless plating. This process is reportedly performed to ensure adequate bonding of the electroless copper layer to the resinous substrate. However, it is reported in this patent that a final step in the manufacture of the printed wiring board must be a surface treatment of the resin substrate that is located between the copper circuitry. This final step must be performed to remove remaining catalyst that otherwise would reduce the electrical resistance between the copper circuitry. This additional step performed with hydrazine hydrate, a known carcinogen, adds not only additional complexity to the process but since its intent is to etch the surface of the resin substrate a potential side effect is that undercutting of the substrate around the copper-circuitry will occur causing a weakened bond between the substrate and the copper circuitry, this would especially be true for high density circuitry having very narrow cross-sections.
Although obvious progress has been made in the industry toward reducing the spacing between features on printed wiring boards it is acknowledged that further improvements in the art must be made in order to meet existing and future designs. For example, in 1965 high density printed wiring boards were considered to be those having conductor lines and spaces of 12 mils (0.012 inches), by 1980 that value had been reduced to 6 mils, by 1988 to 5 mils, and by 1998 to 3 mils.
With regard to the discussion hereinabove, it is the intent of this invention to provide a process that will further allow decreasing the spacing of copper features on printed wiring boards. This process is also useful when the printed wiring boards contain through holes with a high aspect ratio.
Another intent of this invention is to provide high density printing wiring boards that possess microelectronic features that exhibit excellent adhesion to the substrate and are electrically isolated from each other.
It is further the intent of this invention to provide a process that is efficient, contains minimal operating steps, and utilizes minimal raw materials thereby minimizing waste production.
These attributes, as well as others, are achieved by simplifying the process necessary for electroless plating and employing an extremely thin commoning layer as part of the semi-additive process for manufacturing printed wiring boards. This thin commoning layer is applied by electroless plating of copper onto a treated substrate. The electroless plating process in the present invention does not rely on either a resinous adhesive layer and a related baking process or an accelerator step as required in the prior art to obtain acceptable adhesion. Furthermore, since the commoning layer is extremely thin, it can be easily etched after the copper features have been fabricated so that no protection of the features (i.e. solder, gold/nickel or other metal mask) is required. Lastly, after the commoning layer is removed no further treatment of the substrate base is required to obtain electrical isolation between the copper features, even at high voltage (e.g., 500 Volts).
Generally stated, the present invention teaches a simplified process for fabricating high density printed wiring boards using a semi-additive process comprising the following steps:
a) providing a dielectric substrate
b) laminating, under pressure, a copper foil to at least one outermost lateral surface of said dielectric substrate,
c) completely removing said copper foil from said outermost surface of said dielectric substrate to create an irregular outermost lateral surface on said dielectric substrate,
d) forming vertical angle through-holes and blind holes into said dielectric substrate,
e) applying a conditioner to the irregular outermost surface to facilitate the later seeding process,
f) applying a catalyst to said irregular outermost surface, through-hole surface and blind hole surface of said dielectric substrate for the purpose of applying subsequently coated layers,
g) electrolessly plating a uniform copper commoning layer on said catalyst,
h) applying a photoresist to the outermost lateral surface of said copper commoning layer,
i) irradiating said photoresist, through a mask having printed circuit features, and developing said photoresist to generate multiple discontinuities in said photoresist, thus image wise revealing areas of said outermost surface of said copper commoning layer,
j) electroplating copper onto: said exposed outermost surfaces of said commoning bar within said multiple discontinuities of said photoresist; said through hole surfaces; and said blind hole surfaces, for the purpose of generating multiple copper features and plated holes, said multiple copper features and plated holes being electrically connected to each other via association with said copper commoning layer,
k) removing unexposed photoresist from step h) to uncover remaining said outermost surface of said copper commoning layer, and
l) etching said remaining copper commoning layer in areas having said uncovered outermost surfaces for the purpose of creating electrical discontinuities between each of said multiple copper features and plated holes.